1. Field of the Invention
The present invention relates to a semiconductor element used for a nonvolatile semiconductor storage device or the like, a semiconductor storage device using the same, a data writing method thereof, a data reading method thereof and a manufacturing method of those.
2. Description of the Related Art
A nonvolatile random access memory (NVRAM) in which even if the power is turned off, the immediately preceding memory is held and a random access can be made is regarded as promising as a device to form the base of ubiquitous society and in the field of personal identification or security.
Among various nonvolatile RAMs, a nonvolatile memory in which a ferroelectric having spontaneous polarization is used for a dielectric layer of a capacitor is called as ferroelectric random access memory (FeRAM). The FeRAM is expected as a next-generation memory in the mobile field, due to the low power consumption.
The FeRAM currently put to practical use is a 1T1C (1 transistor 1 capacitor) type FeRAM including one cell selection transistor and one data storage ferroelectric capacitor. Even if the power is turned off, since an electric charge remains in the ferroelectric capacitor, the 1T1C-type FeRAM can be used as a nonvolatile storage element.
Patent document 1: JP-A-9-134974
Non-patent document 1: Hiroshi Ishiwara, “Current Status of Development of Transistor-type Ferroelectric Memory and Future Prospects”, The Journal of the Institute of Electronics, Information and Communication Engineers, Vol. 88, No. 4, 2005
Non-patent document 2: Yoshihiro Arimoto, Hiroshi Ishiwara, “Current Status of Ferroelectric Random-Access Memory”, Reprinted from Materials Research Society MRS Bulletin, Vol. 29, No. 11, November 2004
As described above, in the 1T1C-type FeRAM, one transistor and one ferroelectric capacitor are required in one memory cell, in order to form the memory cell in the FeRAM, a formation region of considerable size is required. Further, since the quantity of electric charge stored in the ferroelectric capacitor is proportional to the electrode area of the ferroelectric capacitor, when the scaling issue of the FeRAM is advanced, the quantity of electric charge necessary for memory storage can not be kept. That is, it is difficult to form a large density of 1T1C-type FeRAM.
In order to solve the problem in the scalability issue of the FeRAM, there is proposed a method in which a 1T (1 transistor)-type FeRAM of an FET-type system is used instead of the 1T1C-type FeRAM. In the FET-type FeRAM, a gate insulating film is formed of a ferroelectric. This configulatin make possible to use nondestructive readout. With the development of the scalability of a transistor, the area of a memory cell can be reduced. Thus, the FET-type FeRAM has an advantage to the 1T1C-type FeRAM in the scaling capability. However, in the FET-type FeRAM, under present circumstances, a voltage for writing data into a memory cell or reading data stored in the memory cell is high, and the reliability of a gate insulating film is low. Accordingly, the FET-type FeRAM is inferior to the current 1T1C-type FeRAM in retention characteristics indicating the memory storage performance and disturbance characteristics at the time of memory cell selection, and it has not been put to practical use.
A typical FET-type 1T FeRAM has a structure in which a gate insulating film (I), a ferroelectric film (F) and an electrode film (M) are stacked over a channel region of a semiconductor substrate (S) in which a source region and a drain region are formed. The FET having this structure is called an MFIS-type FET. In the FET-type 1T FeRAM, by using a fact that an on current and an off current between the source and drain are different by several digits according to the polarization direction of the ferroelectric film, it is read out whether the stored data is “0” or “1”.
FIG. 27 is a view for explaining data writing of a memory array of an FET-type 1T FeRAM. As shown in FIG. 27, the memory array of the FET-type 1T FeRAM includes plural memory cells arranged in a matrix form. In the memory array of the FET-type 1T FeRAM, at the time of data writing, for example, +V (V) is applied to a word line 151 connected to a gate electrode of a selected cell 150, and for example, 0 (V) is applied to a bit line 153 connected to a drain electrode. At that time, +(⅓)V (V) is applied to word lines 151 connected to gate electrodes of non-selected cells 152 and 154, and for example, +(⅔)V (V) is applied to bit lines 153 connected to drain electrodes thereof. That is, it is necessary to apply the voltage to the gate electrodes of all non-selected cells.
By this, the voltage of +V (V) is applied to the ferroelectric film of the FeRAM of the selected cell 150. The voltage of +(⅓)V (V) is applied to the ferroelectric film of the FeRAM of the non-selected cell 154 connected to one of the word line 151 and the bit line 153 to which the selected cell 150 is connected. The voltage of −(⅓)V (V) is applied to the ferroelectric film of the FeRAM of the non-selected cell 152 connected to the word line 151 or the bit line to which the selected cell 150 is not connected. Accordingly, electric power is consumed also in the non-selected cells 152 and 154 by leak current, and further, since the voltage is applied to all the bit lines and word lines at each writing of one bit, when the cell size becomes large, charging/discharging current of these wiring lines becomes enormous. As stated above, in the semiconductor storage device including the FET-type 1T FeRAM, it is difficult to reduce power consumption.
FIG. 28A and FIG. 28B are views for explaining data reading of the memory array of an n-type FET-type 1T FeRAM. In an MFIS-type FET, in order to hold data for a long period, in the case where 0 (V) is applied to a gate electrode, it is necessary that a difference in the magnitude of a current flowing between a source and a drain is realized according to the polarization direction of a ferroelectric film. FIG. 28A shows a parallel memory array, and FIG. 28B shows a serial memory array. As shown in FIG. 28A, in the parallel memory array in which plural source electrodes are connected to each other and plural drain electrodes are connected to each other, at the time of data reading, a voltage of −V (V) is applied to the gate electrodes of all non-selected cells 152 to cause the non-selected FET to have high resistance, and 0(V) is applied to the gate electrode of a selected cell 150 to read the magnitude of the current flowing between the source and drain of the selected FET from a peripheral circuit. On the other hand, as shown in FIG. 28B, in the serial memory array in which the source electrode and drain electrode of adjacent FET-type 1T FeRAMs are connected, +V (V) is applied to gate electrodes of all non-selected cells 152 to cause the non-selected FETs to have low resistance, and 0 (V) is applied to the gate electrode of a selected cell 150 to read information of the magnitude of current flowing between the source and drain of the selected FET from a peripheral circuit.
As stated above, in the FET-type 1T FeRAM, at the time of writing and reading of data, since it is necessary to apply the predetermined voltages to both the selected cell and the non-selected cell, it is difficult to reduce the power consumption of the semiconductor storage device. Besides, a possibility that the memory data of the non-selected cell is rewritten becomes high, and the reliability is low.
As is apparent from the above description, the 1T1C-type FeRAM has the problem that the scaling is difficult. Besides, the FET-type 1T FeRAM has the problem that the retention characteristics and the disturb characteristics as the memory element are not satisfactory. Besides, the FET-type 1T FeRAM has the problem that it is difficult to reduce the power consumption of the semiconductor storage device.